Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

What are the differences among direct mapping, associative mapping and set-associative mapping?

Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

By Showing the major components of a CPU, briefly describe how a CPU works.

How can processor performance be evaluated? Explain.

What do you know about fetch-execute cycle? Define MBR and MAR.

Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

What do you know about fetch-execute cycle? Define MBR and MAR.

What do you know about fetch-execute cycle? Define MBR and MAR.

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

What do you know about fetch-execute cycle? Define MBR and MAR.

How can processor performance be evaluated? Explain.

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

Describe the multiplexed bus with advantages and disadvantages.

Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 20 vacuum tubes?

Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 20 vacuum tubes?

The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 20 vacuum tubes?

Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 20 vacuum tubes?

Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

When a block that is resident in the cache is to be replaced, there are two cases to consider. Describe the write through and write back.

Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

When a block that is resident in the cache is to be replaced, there are two cases to consider. Describe the write through and write back.

Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide ?

Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

Analyze the geometric depiction of 4-bit numbers for 2's Complement Integers.

Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

The hypothetical machine of the Figure (given at right side) also has two I/O instructions: 0011 Load AC from I/O 0011 Store AC to I/O In these cases, the 12-bit address identifies a particular I/O device. Show the program Execution for the following program: a) Load AC from device 5. b) Add contents of memory location 940. c) Store AC to device 6. Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.

Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide ?

What are the four main components of any general-purpose computer?

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

We would like to design a cache of 64kByte. Main memory is 16Mbytes. Cache block is 4 bytes (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

How to determine the performance of a processor? Explain.

It is possible to build a computer which uses only static RAM. This would be very fast and would need no cache. Analyze its cost.

Analyze the step(s): (i) no interrupt, (ii) interrupt pending.

Analyze the concept of "Write Back" in order to avoid the bottleneck of "Write Through".

What are the differences among direct mapping, associative mapping and set-associative mapping?

What is instruction? Mention the elements of an instruction.

Distinguish between 0-addresses, 2-addresses, 3-addresses instruction with the example a = b + c.

The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 10 vacuum tubes?

Von Neumann computer architecture is the basic computer architecture for the modern computer. Explain this.

Interrupts are provided primarily as a way to improve processing efficiency. For example, most external devices are much slower than the processor. Describe with figure(s) for the following: (i) No interrupt, (ii) short I/O wait interrupt, (iii) long I/O wait interrupt.

Discuss about the memory hierarchy and typical cache organization.

Write notes on associative mapping function related to cache memory.

The simplest technique for replacement policy in cache is called write through. Using this technique, all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid. Any other processor-cache module can monitor traffic to main memory to maintain consistency within its own cache. The main disadvantage of this technique is that it generates substantial memory traffic and may create a bottleneck. An alternative technique, known as write back, minimizes memory writes. Discuss the term "write back".

What is the purpose of using addressing mode techniques in computer?

In interrupt handler, analyze the step(s): (i) no interrupt, (ii) interrupt pending.

Analyze the concept of "Write Back" in order to avoid the bottleneck of "Write Through".

What are the differences among direct mapping, associative mapping and set- associative mapping?

Describe how an assembler works with its two phases.

Analyze the step(s): (i) no interrupt, (ii) interrupt pending.

Analyze the concept of "Write Back" in order to avoid the bottleneck of "Write Through".

What are the differences among direct mapping, associative mapping and set-associative mapping?

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 KBytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. Find the number of bits in the tag field for an address.

Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 KB. The average seek time is 8 ms, the track-to-track access time is 1.5 ms, and the drive rotates at 3600 rpm. Successive tracks in a cylinder can be read without head movement. i) What is the disk capacity? ii) What is the burst transfer rate? Estimate the time required to transfer a 5-MB file.

Define pipelining. Show the timing diagram of pipelining.

Constructing a computer that utilizes only static RAM is technically feasible. Such a system would offer exceptional speed and eliminate the need for cache memory. An assessment of its cost implications is required.

Display the synchronous system bus read/write timing diagram.

In cache memory, overwriting a block before main memory is updated should be avoided. With "Write Through", every write updates both cache and main memory, increasing traffic and slowing performance. To reduce this bottleneck. consider using "Write Back", which updates main memory only when a cache block is replaced. Analyze the concept of "Write Back" in order to avoid the bottleneck of "Write Through".

How can processor performance be evaluated? Explain.

In Direct Memory Access (DMA) operation, describe about "Cycle Stealing"

I/O is much slower than the CPU, so the CPU can remain idle even in multi programming systems. What solutions exist to synchronize them?

Distinguish between 3-addresses, 2-addresses, 1-address, and 0-addresses instruction with the example a = b + c.

8080 has 16 bit address bus. Then how much memory space it will provide?

Let's design a cache of 64KByte. Main memory is 16Mbytes. Cache block is 4 types (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

Von Neumann computer architecture is the basic computer architecture for the modern computer. Explain this.

In Direct Memory Access (DMA) operation, describe about "Cycle Stealing"

Briefly describe the data processing and data movement functions of computer.

Explain the trade-off (more or less) of the number of addresses for instruction.

While processor power has raced ahead at breakneck speed, other critical components of the computer have not kept up. The result is a need to look for performance balance: an adjusting of the organization and architecture to compensate for the mismatch among the capabilities of the various components. Nowhere is the problem created by such mismatches more critical than in the interface between processor and main memory. There are a number of ways that a system architect can attack this problem, all of which are reflected in contemporary computer designs. Analyze to solve these mismatch between processor and main memory.

Distinguish between traditional bus architecture and high performance bus architecture.

What are the differences among direct mapping, associative mapping, and set-associative mapping?

Draw and explain the block diagram of the hardware for implementing the addition and subtraction operation.

RAID 4 involves a write penalty when an I/O write request of small size is performed. Each time that a write occurs, the array management software must update not only the user data but also the corresponding parity bits. Consider an array of five drives in which X0 through X3 contain data and X4 is the parity disk. Suppose that a write is performed that only involves a strip on disk X1. How data can be reconstructed for RAID 4?

In Direct Memory Access (DMA) operation, describe about "Cycle Stealing".

How can you classify computer instructions? Explain your idea about logical and bit manipulation instruction.

How much memory space 8080 will provide that has 16 bit address bus?

Let's design a cache of 64KByte. Main memory is 16Mbytes. Cache block is 4 bytes (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

Von Neumann computer architecture is the basic computer architecture for the modern computer. Explain this.

In Direct Memory Access (DMA) operation, describe about "Cycle Stealing"

Distinguish between 0-addresses, 2-addresses, 3-addresses instruction with the example a = b + c.

The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 10 vacuum tubes?

Let's design a cache of 64kByte. Main memory is 16Mbytes. Cache block is 4 bytes (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

Von Neumann computer architecture is the basic computer architecture for the modern computer. Explain this.

In Direct Memory Access (DMA) operation, describe about "Cycle Stealing"

Briefly describe the data processing and data movement functions of computer.

Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide ?

We would like to design a cache of 64kByte. Main memory is 16Mbytes. Cache block is 4 bytes (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

Describe the multiplexed bus with advantages and disadvantages..

In I/O controller in computer architecture, O/S works as a resource manager. Discuss this statement with suitable figure(s).

What are the key elements of an operating system in computer architecture and organization? Explain with relevant diagrams.

Discuss the concept of associate mapping address in main memory while designing a cache memory.

Write short notes on the following: i) Hit time ii) Miss penalty

Show the Asynchronous timing diagram for system bus Read/Write cycle.

List and briefly define three (03) techniques for performing I/O.

Describe the multiplexed bus with advantages and disadvantages.

Describe O/S as a resource manager in I/O controller.

Briefly describe the instruction cycle of program execution.

Distinguish between computer architecture and computer organization.

Instruction processing consists of two steps: The processor reads (fetches) instructions from memory one at a time and executes each instruction. Program execution consists of repeating the process of instruction fetch and instruction execution. Distinguish between fetch cycle and instruction cycle with suitable figures.

Discuss with figures: Timing of Asynchronous Bus Operations

Describe O/S as a resource manager in I/O controller.

Regarding Cache design, write short notes on the following: i) Hit time ii) Miss penalty

Describe with figure: Asynchronous timing diagram for system bus Read/Write cycle.

List and briefly define three (03) techniques for performing I/O.

Describe the multiplexed bus with advantages and disadvantages.

Describe O/S as a resource manager in I/O controller.

How Stack is organized in CPU? With proper block diagram, describe following types of stack: (i) Register and (ii) Memory Stack.

Write two short notes from the below: i) Op-code, ii) Machine Language, iii) Vector Processor.

Write short notes on the following: i) Hit time ii)Miss penalty

Show the Asynchronous timing diagram for system bus Read/Write cycle.