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University of Barishal

Department of Computer Science and Engineering

1st Mid Exam

Course Title: Computer Architecture and Organization (CSE-2203)

Semester: 4th | Session: 22-23

Time: 100 minutes | Marks: 60.00

Exam Date: September 18, 2025

View 151 Topic-wise Questions for this Course

Question: Answer all

1.

1) What do you know about fetch-execute cycle? Define MBR and MAR.

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Topics: Fetch–Decode–Execute Cycle , MAR (Memory Address Register) , MBR (Memory Buffer Register) , Memory Operations Solution is Coming!
3 Marks
2) What are the differences among direct mapping, associative mapping and set-associative mapping?

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Topics: Cache Memory Mapping Techniques Solution is Coming!
2 Marks
3) Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

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Topics: Hit Ratio and Miss Penalty , Memory Hierarchy Solution is Coming!
10 Marks
4) Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

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Topics: Interrupt Handling , Interrupts and Interrupt Service Routines (ISR) Solution is Coming!
10 Marks
5) Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

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Topics: 8080 Microprocessor , Memory Addressing , Memory and I/O , System Bus Solution is Coming!
10 Marks
6) Describe the bottleneck for Cache Design.

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Topics: Cache Memory , Memory Bottlenecks Solution is Coming!
7 Marks
7) Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

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Topics: Cache Memory , Cache Memory Mapping Techniques , Hit Ratio and Miss Penalty Solution is Coming!
8 Marks
8) Describe the multiplexed bus with advantages and disadvantages.

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Topics: System Bus Solution is Coming!
4 Marks
9) How can processor performance be evaluated? Explain.

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Topics: Computer Architecture , Processor Performance Solution is Coming!
6 Marks
View 151 Topic-wise Questions for this Course

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Uploaded By: Ritu Akter Samia Sept. 18, 2025, 7:25 p.m.
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