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University of Barishal

Department of Computer Science and Engineering

Final Exam

Course Title: Computer Architecture and Organization (CSE-2203)

Semester: 4th | Session: 21-22

Time: 180 minutes | Marks: 60.00

Course Teacher: Dr. Md Manjur Ahmed

Exam Date: July 22, 2025

Answer any Five(5) Questions from the followings.

1.


a) Constructing a computer that utilizes only static RAM is technically feasible. Such a system would offer exceptional speed and eliminate the need for cache memory. An assessment of its cost implications is required.

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4 Marks
b) Analyze the structure of the "Control Unit".

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2 Marks
c) Differentiate the terms architecture and organization in terms of computer.

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2 Marks
d) Figure 1 illustrates a partial program execution, showing the relevant portions of memory and CPU registers. The program fragment shows the contents of the memory word at address 940 to the contents of the memory word at address 941 and stores the result in the latter location. Continue the program execution steps until program counter (PC) is 302.

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4 Marks
2.


a) Display the synchronous system bus read/write timing diagram.

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6 Marks
b) Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide ?

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2 Marks
c) In interrupt cycle, analyze the step(s) if: (i) no interrupt, (ii) interrupt pending.

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4 Marks
3.


a) In cache memory, overwriting a block before main memory is updated should be avoided. With "Write Through", every write updates both cache and main memory, increasing traffic and slowing performance. To reduce this bottleneck. consider using "Write Back", which updates main memory only when a cache block is replaced. Analyze the concept of "Write Back" in order to avoid the bottleneck of "Write Through".

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4 Marks
b) We would like to design a cache of 64kByte. Main memory is 16Mbytes. Cache block is 4 bytes (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

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8 Marks
4.


a) Examine the pros and cons of CD-ROMs.

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2 Marks
b) Distinguish between RAID 4 and RAID 5.

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3 Marks
c) Regarding internal memory, analyze the error correction methods and its correcting code function.

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4 Marks
d) Discuss about Synchronous DRAM (SDRAM) as external memory.

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3 Marks
5.


a) How can processor performance be evaluated? Explain.

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2 Marks
b) Describe the multiplexed bus with advantages and disadvantages..

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3 Marks
c) The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 10 vacuum tubes?

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4 Marks
d) Discuss the concept of von Neumann computer architecture.

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3 Marks
6.


a) In Direct Memory Access (DMA) operation, describe about "Cycle Stealing"

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6 Marks
b) In I/O controller in computer architecture, O/S works as a resource manager. Discuss this statement with suitable figure(s).

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6 Marks
7.


a) I/O is much slower than the CPU, so the CPU can remain idle even in multi programming systems. What solutions exist to synchronize them?

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4 Marks
b) What are the key elements of an operating system in computer architecture and organization? Explain with relevant diagrams.

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4 Marks
c) Analyze the geometric depiction of 4-bit numbers for 2's Complement Integers.

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4 Marks
8.


a) Distinguish between 3-addresses, 2-addresses, 1-address, and 0-addresses instruction with the example a = b + c.

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8 Marks
b) Discuss the concept of associate mapping address in main memory while designing a cache memory.

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4 Marks

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Contributors of this Question:

Role Name Date
Prepared By (Teacher): Dr. Md Manjur Ahmed July 22, 2025
Uploaded By: Margia Rowshon July 22, 2025, 2:56 p.m.
Converted By (Img/PDF to Text): Baishakhi Bir Nov. 19, 2025, 8:51 p.m.
Reviewed By: Obaydul Hasan Nayeem Nov. 19, 2025, 11:18 p.m.