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University of Barishal

Department of Computer Science and Engineering

Final Exam

Course Title: Computer Architecture and Organization (CSE-2203)

Semester: 4th | Session: 20-21

Time: 180 minutes | Marks: 60.00

Course Teacher: Dr. Md Manjur Ahmed

Exam Date: November 3, 2024

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Answer any Five (5) Questions from the Followings.

1.

a) How to determine the performance of a processor?

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2 Marks
b) Differentiate between SRAM and DRAM.

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4 Marks
c) Write short notes on the following: i) Hit time ii)Miss penalty

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6 Marks
2.

a) Analyze the step(s): (i) no interrupt, (ii) interrupt pending.

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4 Marks
b) The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 10 vacuum tubes?

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4 Marks
c) Show the Asynchronous timing diagram for system bus Read/Write cycle.

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4 Marks
3.

a) Analyze the concept of "Write Back" in order to avoid the bottleneck of "Write Through".

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4 Marks
b) Let's design a cache of 64kByte. Main memory is 16Mbytes. Cache block is 4 bytes (2 bit word identifier) and rest of bits is block identifier. Use the concept of direct mapping address.

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8 Marks
4.

a) What are the differences among direct mapping, associative mapping and set-associative mapping?

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4 Marks
b) Assume that there are three (03) small caches, each consisting of eight (08) one-word blocks. One cache is fully associative, a second is two-way set associative, and third is direct mapped. Now, find the number of misses for each cache organization given the following sequence of block address: 0, 8, 0, 6, 8

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5 Marks
c) List and briefly define three (03) techniques for performing I/O.

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3 Marks
5.

a) A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 KBytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. Find the number of bits in the tag field for an address.

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3 Marks
b) Von Neumann computer architecture is the basic computer architecture for the modern computer. Explain this.

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5 Marks
c) Describe the multiplexed bus with advantages and disadvantages.

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4 Marks
6.

a) Describe the necessity of I/O modules?

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2 Marks
b) In Direct Memory Access (DMA) operation, describe about "Cycle Stealing"

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6 Marks
c) Describe O/S as a resource manager in I/O controller.

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4 Marks
7.

a) Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 KB. The average seek time is 8 ms, the track-to-track access time is 1.5 ms, and the drive rotates at 3600 rpm. Successive tracks in a cylinder can be read without head movement. i) What is the disk capacity? ii) What is the burst transfer rate? Estimate the time required to transfer a 5-MB file.

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4 Marks
b) Briefly describe the data processing and data movement functions of computer.

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3 Marks
c) Briefly describe the instruction cycle of program execution.

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5 Marks
8.

a) Define pipelining. Show the timing diagram of pipelining.

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4 Marks
b) Explain Processor with an accumulator register.

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3 Marks
c) Briefly describe the data processing and data movement functions of computer.

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5 Marks

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View 151 Topic-wise Questions for this Course

Contributors of this Question:

Role Name Date
Prepared By (Teacher): Dr. Md Manjur Ahmed Nov. 3, 2024
Uploaded By: Baishakhi Bir Nov. 6, 2024, 9:26 a.m.
Converted By (Img/PDF to Text): Baishakhi Bir Nov. 19, 2025, 10:49 p.m.
Reviewed By: Obaydul Hasan Nayeem Nov. 19, 2025, 11:33 p.m.
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