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University of Barishal

Department of Computer Science and Engineering

1st Mid Exam

Course Title: Computer Architecture and Organization (CSE-2203)

Semester: 4th | Session: None

Time: 50 minutes | Marks: 60.00

Course Teacher: Dr. Md. Manjur Ahmed

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1.

1) The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 20 vacuum tubes?

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10 Marks
2) Consider a two-level cache with access time 5 nsec and 80 nsec respectively. If the hit ratio is 95% and 75% respectively in the two caches and main memory access time is 250 nsec. What is the effective access time?

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10 Marks
3) Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

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10 Marks
4) Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide?

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5 Marks
5) Describe the bottleneck for Cache Design.

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10 Marks
6) How to determine the performance of a processor? Explain.

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5 Marks
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Contributors of this Question:

Role Name Date
Prepared By (Teacher): Dr. Md. Manjur Ahmed N/A
Uploaded By: Onebyzero Edu (Test User) Aug. 1, 2024, 4:28 p.m.
Converted By (Img/PDF to Text): Subrina Jahan Meem Nov. 16, 2025, 10:58 a.m.
Reviewed By: Obaydul Hasan Nayeem Nov. 16, 2025, 12:35 p.m.
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