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University of Barishal

Department of Computer Science and Engineering

Final Exam

Course Title: Computer Architecture and Organization (CSE-2203)

Semester: 4th | Session: 18-19

Time: 180 minutes | Marks: 60.00

Course Teacher: Dr. Md. Manjur Ahmed

View 151 Topic-wise Questions for this Course
1.

a) The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 10 vacuum tubes?

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6 Marks
b) Explain Moor's Law in Computer architecture.

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3 Marks
c) Distinguish between computer architecture and computer organization.

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3 Marks
2.

a) Von Neumann computer architecture is the basic computer architecture for the modern computer. Explain this.

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3 Marks
b) While processor power has raced ahead at breakneck speed, other critical components of the computer have not kept up. The result is a need to look for performance balance: an adjusting of the organization and architecture to compensate for the mismatch among the capabilities of the various components. Nowhere is the problem created by such mismatches more critical than in the interface between processor and main memory. There are a number of ways that a system architect can attack this problem, all of which are reflected in contemporary computer designs. Analyze to solve these mismatch between processor and main memory.

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5 Marks
c) Instruction processing consists of two steps: The processor reads (fetches) instructions from memory one at a time and executes each instruction. Program execution consists of repeating the process of instruction fetch and instruction execution. Distinguish between fetch cycle and instruction cycle with suitable figures.

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4 Marks
3.

a) Interrupts are provided primarily as a way to improve processing efficiency. For example, most external devices are much slower than the processor. Describe with figure(s) for the following: (i) No interrupt, (ii) short I/O wait interrupt, (iii) long I/O wait interrupt.

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3 Marks
b) Distinguish between traditional bus architecture and high performance bus architecture.

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4 Marks
c) Discuss with figures: Timing of Asynchronous Bus Operations

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5 Marks
4.

a) Discuss about the memory hierarchy and typical cache organization.

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b) What are the differences among direct mapping, associative mapping, and set-associative mapping?

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3 Marks
c) Discuss the features of Synchronous DRAM (SDRAM).

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5 Marks
5.

a) Write notes on associative mapping function related to cache memory.

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6 Marks
b) Draw and explain the block diagram of the hardware for implementing the addition and subtraction operation.

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6 Marks
6.

a) The simplest technique for replacement policy in cache is called write through. Using this technique, all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid. Any other processor-cache module can monitor traffic to main memory to maintain consistency within its own cache. The main disadvantage of this technique is that it generates substantial memory traffic and may create a bottleneck. An alternative technique, known as write back, minimizes memory writes. Discuss the term "write back".

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6 Marks
b) RAID 4 involves a write penalty when an I/O write request of small size is performed. Each time that a write occurs, the array management software must update not only the user data but also the corresponding parity bits. Consider an array of five drives in which X0 through X3 contain data and X4 is the parity disk. Suppose that a write is performed that only involves a strip on disk X1. How data can be reconstructed for RAID 4?

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6 Marks
7.

a) Distinguish between RAID 4 and RAID 5.

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4 Marks
b) In Direct Memory Access (DMA) operation, describe about "Cycle Stealing".

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5 Marks
c) Describe O/S as a resource manager in I/O controller.

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3 Marks
8.

a) What is the purpose of using addressing mode techniques in computer?

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3 Marks
b) How can you classify computer instructions? Explain your idea about logical and bit manipulation instruction.

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5 Marks
c) Explain interrupt driven I/O technique.

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4 Marks
View 151 Topic-wise Questions for this Course

Contributors of this Question:

Role Name Date
Prepared By (Teacher): Dr. Md. Manjur Ahmed N/A
Uploaded By: Onebyzero Edu (Test User) Aug. 1, 2024, 4:23 p.m.
Converted By (Img/PDF to Text): Subrina Jahan Meem Nov. 16, 2025, 10:45 a.m.
Reviewed By: Obaydul Hasan Nayeem Nov. 16, 2025, 1:44 p.m.
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