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University of Barishal

Department of Computer Science and Engineering

1st Mid Exam

Course Title: Computer Architecture and Organization (CSE-2203)

Semester: None | Session: 20-21

Time: 50 minutes | Marks: 40.00

Course Teacher: Dr. Md Manjur Ahmed

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1.

1) Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, why is this representation "wasteful" and what range of integer values could we represent using the 20 vacuum tubes?

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10 Marks
2) Suppose three interrupt handlers A, B and C (having priority level A>B>C) with Interrupt Service Routine (ISR) 10, 30 and 20 respectively. Graphically show the transfer of control for interrupt sequence of C, A and B at time t=10, 25 and 45 respectively.

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10 Marks
3) Regarding Address Bus, Bus width determines maximum memory capacity of system. For example, 8080 has 16 bit address bus. Then how much memory space it will provide ?

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5 Marks
4) The hypothetical machine of the Figure (given at right side) also has two I/O instructions: 0011 Load AC from I/O 0011 Store AC to I/O In these cases, the 12-bit address identifies a particular I/O device. Show the program Execution for the following program: a) Load AC from device 5. b) Add contents of memory location 940. c) Store AC to device 6. Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.

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10 Marks
5) What are the four main components of any general-purpose computer?

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5 Marks

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Contributors of this Question:

Role Name Date
Prepared By (Teacher): Dr. Md Manjur Ahmed N/A
Uploaded By: Onebyzero Edu (Test User) Aug. 1, 2024, 4:19 p.m.
Converted By (Img/PDF to Text): Baishakhi Bir Nov. 20, 2025, 12:57 a.m.
Reviewed By: Obaydul Hasan Nayeem Nov. 20, 2025, 10:16 a.m.
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